In the population of integrated circuit chip carriers, including thermally conductive modules, ceramic substrates, and polymeric substrates, it is necessary to minimize the shipment of modules with defective integrated circuit chips, while minimizing the cost of testing and replacement.
Integrated circuit chips are subjected to various wafer level tests during various stages of fabrication prior to dicing. However, after dicing it is particularly difficult and expensive to test integrated circuit chips. One reason is that an integrated circuit chip must be tested through its pins and contacts or pads before populating of the carrier, card, board, or the like.
Typically, integrated circuit chips are attached to a chip carrier, thermally conductive module chip carrier, circuit card or board, e.g., by solder bonding, brazing, controlled collapse chip connect, wire lead bonding, metal bump bonding, tape automated bonding, or the like.
The chip is then tested as part of an assembly and when a fault is found, the chip is removed from the card or board. This is not a simple "desoldering" step, especially in the case of high I/O density chips, encapsulation chip connect technologies, and multi-chip modules. In these instances the defective chip is removed, the chip site redressed, and a new chip installed for testing. In the case of a polymeric substrate, redressing the chip site might include milling.
Dendritic Chip Testers.
"High Performance Test System", IBM Technical Disclosure Bulletin, Volume 33, No. 1A (June 1990), pp 124-125, describes a test system for ULSI integrated circuit memory and logic chips. In the described method, a first silicon wafer "test board" has metallization complementary to the metallization of the second silicon wafer to be tested. The second silicon wafer has C4 (controlled collapse chip connection) Pb/Sn solder balls on the contacts. The first and second silicon wafers have substantially flat and substantially parallel surfaces, and are said to require a minimum of compressive force for testing.
"New Products Test Interposer" Research Disclosure, January 1990, Number 309 (Kenneth Mason Publications Ltd., England) describes a method for fabricating an interposer-type test head to perform electrical testing of printed circuit cards and boards prior to component assembly. The test interposer is built as a mirror image circuit of the circuit to be tested. However, only the points to be tested, as lands and pads, are present. Circuit lines are not present. The test interposer pads are coated with a dendritic material to make electrical contact to the corresponding points on the printed circuit component to be tested. The circuit board or card and the tester are then brought into contact for testing.
Testers.
Compressive type testers are described generally in U.S. Pat. No. 4,716,124 to Yerman et al. for TAPE AUTOMATED MANUFACTURE OF POWER SEMICONDUCTOR DEVICES, U.S. Pat. No. 4,820,976 to Brown for TEST FIXTURE CAPABLE OF ELECTRICALLY TESTING AN INTEGRATED CIRCUIT DIE HAVING A PLANAR ARRAY 0F CONTACTS, and U.S. Pat. No. 4,189,825 to Robillard et al. for INTEGRATED TEST AND ASSEMBLY DEVICE.
U.S. Pat. No. 4,189,825 to Robillard et al. for INTEGRATED TEST AND ASSEMBLY DEVICE describes a chip of the beam lead type with sharp points on the substrate leads and etched, conical holes in the semiconductor. The semiconductor and conical holes are metallized with a thin, conformal metal film, leaving conical openings in the metallization. These apertures correspond to the sharp points on the substrate leads. According to Robillard et al, the chips may be assembled and tested, with faulty chips removed and replaced before bonding. Bonding is by ultrasonic welding.
Dendritic Connections.
Dendritic connections are described in commonly assigned U.S. Pat. No. 5,137,461 of Bindra et al for SEPARABLE ELECTRICAL CONNECTION TECHNOLOGY. Bindra et al describe separable and reconnectable electrical connections for electrical equipment. Bindra et al's connectors have dendrites characterized by an elongated, cylindrical morphology. These cylindrical dendrites are prepared by a high frequency, high voltage, high current density, pulse plating methodology utilizing a dilute electrolyte. Bindra et al describe the pulsed electro-deposition of Pd from a 10-150 millimolar Pd tetramine chloride, 5 molar ammonium chloride solution at 50 to 450 hertz and 200 to 1100 milliamperes per square centimeter in a pulse plating technique.
Electro-deposition of Pd dendrites is further described in European Patent No. 0054695 and U. S. Pat. No. 4,328,286 (European Patent 0020020)
U.S. Pat. No. 4,328,286 (European Patent 20020) to Crosby for ELECTROPLATING A SUBSTRATE WITH TWO LAYERS 0F PALLADIUM describes producing a low porosity Pd coating for electrical contacts. The Pd coating is prepared by electro-depositing a first layer of Pd from an aqueous bath containing the cationic complex Pd (NH.sub.3).sub.4.sup.++ and free ammonia with supporting anions (Cl.sup.-, Br.sup.-, NH.sub.2 SO.sub.3.sup.-, NO.sub.2.sup.- and NO.sub.3.sup.-) and then electro-depositing a second Pd layer from an aqueous bath containing the anionic complex Pd(NO.sub.2).sub.2.sup.4- with supporting cations.
Commonly assigned European Patent 54695 (published Jun. 30, 1982, granted Sep. 11, 1985, U.S. Application 219660 filed Dec. 24, 1980) discloses a method of preparing a Pd electrical contact by electro-deposition from a relatively dilute solution that is sprayed onto a cathode which is located completely outside and above the surface of the solution, which is located in a tank. The solution forms a continuous curtain falling from the bottom end of the cathode back into the tank. A higher electric current than usual is used in the deposition process. The dendrites obtained have a larger cross-section than those obtained in conventional processes.
Conclusion.
The art has failed to provide a means for rapid, reproducible, low cost, high throughput testing of integrated circuit chips.